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Articles for the Week of Feb. 26, 2007
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Featured Article
Fast Virtual Prototyping for early software design and verification
This paper describes a simplified and novel approach for fast and easy virtual prototyping which provides a fully functional and accurate platform for the embedded software developer. This platform enables the software developer to execute the same binary image on the virtual platform as he would on the real hardware. The virtual platform, thus developed, can also be used for meaningful development of newer software features and upgrades, and will carry a lot of value for software development. |
Additional Articles |
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System simulation speeds application development |
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Consider OTP memory for IC antipiracy |
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The challenges of next-gen multicore networks-on-chip systems: Part 4 |
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Articles for the Week of Feb. 22, 2007
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Featured Article
Using a Versatile, Independent IP Platform for SoC Design
This paper shows how companies adopting an IP platform approach can maximize the benefits of their investment by choosing a flexible, versatile platform suitable for a variety of projects. Major points to consider are illustrated through one such platform, the PIP-AMBA from CAST |
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Accelerated IP Model Development |
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Which USB is Right for Your Application? (Part 2) |
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Developing an automotive electrical distribution system Part 1: System design |
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Which version of USB is right for your application? (Part 1) |
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Plan your verification with SystemVerilog |
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Articles for the Week of Feb. 15, 2007
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Featured Article
High Performance Connectivity IP -- Avoiding Pitfalls When Selecting An IP Vendor
In this paper, we will discuss how to select a third party IP vendor, how to verify third party IP, and some of the gotcha's when integrating third party IP, with a special focus on the SerDes-based PHYs for PCI Express and SATA as well as PHYs for USB and DDR2. In addition, we will discuss the impact of 65 nm and 45 nm process effects on yield, we will review the advantages and disadvantages of moving to serial links, we will propose complete vertical integrated solutions, and we will present production testing techniques. |
Additional Articles |
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Designing low-power multiprocessor chips |
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Improve performance and reduce power consumption in mixed-signal designs |
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Can the ARM11 handle DSP? |
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The challenges of next-gen multicore networks-on-chip systems: Part 2 |
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Achieving completeness in IP functional verification |
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Articles for the Week of Feb. 08, 2007
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Featured Article
Fully Digital Implemented Phase Locked Loop
This paper shows an approach for a PLL that only uses digital cell libraries. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the PLL also can be used in a FPGA. One of the most astonishing feature is the possibility to check the whole functionality with a pure digital simulator. So without an analog simulator like Spice performance values like frequency and jitter can be checked. |
Additional Articles |
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SoC boosts speech-recognition systems |
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Getting the most out of ASIC prototyping with FPGAs |
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Designing with Virtex-5 Embedded Tri-Mode Ethernet MACs |
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The challenges of nextgen multicore networks-on-chip systems: Part 1 |
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Articles for the Week of Feb. 01, 2007
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Designing custom embedded multicore processors |
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Programmable accelerators: hardware performance with software flexibility |
