 |
|
Commentary: Fast ASICs with structure (by Clive Maxfield)
Fast ASICs with structure A few months ago (which is equivalent to around 100 years in the world of the average electronics engineer), I penned a column on Structured ASICs (SAs). Like many of the folks I know, these little rapscallions kind of snuck up on me while I wasn't looking, because (a) the vendors had largely been working in stealth mode and (b) prior to a consensus being reached on the SA moniker, anyone who was talking about this concept was using their own internally-developed name. Just to refresh our memories, a structured ASIC is based on the concept of a tile or module which typically contains some generic logic in the form of gates and/or multiplexers and/or lookup tables along with one or more flip-flops/latches. An array (“sea”) of these tiles is then replicated across the face of the device. There are also things like embedded RAM blocks, and other features such as multiple clock doma ins, boundary scan, full internal scan, and BIST are embedded in the basic fabric. The key SA differentiator is that all of the components and the majority of the metallization layers are pre-fabricated, and the resulting wafers are stockpiled awaiting only the finishing touches. Only a limited number of metallization layers have to be defined in order to specify and connect the logic functions in the tiles and to link the tiles themselves into the local and global routing architecture. Now I was aware that some vendors had dipped their toes in the water with rudimentary versions of this technology in the early 1990s, but these experiments quickly disappeared without trace. So I was somewhat surprised to learn that the guys and gals at Lightspeed Semiconductor have actually been working on these little rascals since 1996 (although they've been calling them Modular Array ASICs) and that they are currently on their third generation of devices. 700 MHz for a structured ASIC -- wow! According to Lightspeed, the first-ever true Structured ASIC on the planet was their CosmicArray component, which was implemented at the 0.35 um node and is still in production. This was followed by their Lightning offering at the 0.25 um node, which was itself surpassed by their current state-of-the-art Luminance device. The first SA to be made available to the market at the 0.13 um node (although I'm sure there are others now), the Luminance family provides up to 10 million logic gates and is said to run at up to 700 MHz (which is WAY faster than I thought SAs could go). Lightspeed says that the average cost of developing a reasonably high-end standard cell-based device is around $10 million, which pretty much fits in with what everyone else is saying (this is the total cost involved in taking the chip from the start of the design all the way into production). They also say that by using their Luminance SA, one can shave 6 to 9 months of the develop ment cycle and reduce the cost to only $4 million. If I were heading up a system house and was about to slap some of my hard-earned lucre on the table to develop a new chip, this would certainly make me sit up and take notice! AutoTest and AutoBist One cool aspect of the Lightspeed chips is that there are no user-instantiated test circuits, no design-for-test (DFT) considerations or restrictions, and no requirement for netlist changes with associated performance reductions. For example, the system treats clock trees like any other logic, and if there are any combinational loops the system automatically detects them and inserts buffers to break them and make them testable. Lightspeed's AutoTest tool automatically partitions the design into “logic cones.” The test structures embedded in the fabric allow all of the inputs to each cone to be forced to desired values and all of the outputs from each cone to be observed. Next, their automatic test pattern generation (ATPG) tool called A utoBIST automatically creates test vectors based on the design implementation to exhaustively check each cone. This provides 100% stuck-at-fault tests, all totally transparent to the user. The test tools also allow all clock domains to be run fully asynchronously at speed (for four clock cycles at a time). Not time-to-market, but time-to-money Call me a cynic if you will, but over the last two decades I've become used to EDA vendors equipping long-suffering engineers with the most horrendously convoluted tools and then running for the hills whenever we have any questions. But Lightspeed is trying to sell chips — not tools — so they have a completely different way of doing things. From Lightspeed's point of view as a relatively small company, the cost of deploying tools would be huge — so they don't do it. As they told me, they've never actually had a customer push them to get their hands on their place-and-route tools. Instead, they have a modus operandi that brings tear s of joy to my eyes. All you have to do is to give them your gate-level netlist (or RTL with good timing constraints) and they will give you back a working chip. What? Let's run through that again. Apparently only one customer has gone for the RTL option thus far — the rest have gone the gate-level netlist route — but essentially you throw your logical design over the fence to Lightspeed and they take care of all of the physical implementation portions of the flow. Lightspeed also like to say that you shouldn't think in terms of “time-to-market,” but rather in terms of “time-to-money.” Depending on the size and complexity of your device, once you've provided them with your RTL or gate-level netlist, they can give you a working chip in 6 to 13 weeks (the 13 weeks comes from a recent high-end design that included 1 week of customer verification). I must admit that by this time I was starting to become pretty impressed. But then I pulled myself up and asked the age-old question — “how much does it cost?” In answer, Lightspeed first pointed out that the NRE for a standard cell-based device varies all over the map. If you are a well-known, preferred customer with a huge production run in mind, then the ASIC foundry will bend over backwards and might charge you $600K (the cost of producing the components would be on top of this, of course). Alternatively, if you are a new start-up customer, the foundry might demand $2.5 million or more. Eeeekkk! By comparison, Lightspeed has what seems to me to be an incredibly simple cost model. Their list price NRE for an 0.25 um device is $65K, while the NRE for an 0.13 um chip is $200K. This is for any size component and, as we discussed above, it involves taking your RTL or gate-level netlist and giving you back a working chip almost before you've recovered from your “hurray, we finished our design party!” Well I don't know about you, but I'm definitely impressed, to the extent that I'm awarding an official “Mega-Cool-Beans” to Lightspeed (and I'm sure they would display it proudly on the wall were it to have any form of physical manifestation). Until next time, have a good one! Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max was once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.
|
| |||||||||||||||||
