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How effective use of ESL tools can increase your HW/SW system design productivity
(10/05/07, 12:15:00 AM EDT) -- Embedded.com For several years, the semiconductor industry has not been driven by a single killer application, but by the convergence and consumerization of existing markets. Moreover, the increased complexity that comes with 90nm and smaller geometries has made product development harder and more costly. The net result for engineers is a myriad of severe challenges, including hardware/ software (HW/SW) co-design, power management and verification. An Electronic System Level (ESL) methodology offers a viable solution to these challenges if it includes a clear-cut path to established implementation flows. ESL, which is defined here as design and verification done above the RTL, is used today by most semiconductor and system companies. For years, architects have been writing ESL models to prototype and validate systems. In the past, however, other engineers seldom used these models. What has changed is that ESL languages, tools and methodologies now exist, which fosters reuse and allows the ESL investment to be leveraged across the design process.
 Figure 1: Separation of computation and communication allows for reuse across verification.
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