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By Kiyosi Isihara, Director of Engineering, ViASIC
Courtesy of  EE Times - (07/03/2006 9:00 AM EDT)

A growing number of system-on-chip designs contain configurable sections that can be quickly, easily and inexpensively reprogrammed or respun. With SoC configurability, designers, without worrying about costs, can now get out initial versions of a product before final specs are set, getting hot products to market first. By adding configurable sections, companies can add or change features, fix even insignificant bugs and design different versions of the same part for different markets. Customer-specific features can be quickly added to help win new business.

Hardware fabrics for these configurable sections fall into three categories: field programmable, metal programmable and standard metal.

Field-programmable fabrics use the same basic programmable building blocks as popular FPGAs, using memory for their configurability and offering the ultimate in versatility. Field-programmable fabrics are power-hungry, however, and require 20 to 50 times the chip area of other configurable fabrics. Metal-programmable fabrics are close cousins of legacy gate-array technologies and require three to 12 photomasks to program and route the design. Standard-metal fabrics have preconfigured logic and routing. But instead of a large memory for configurability, standard-metal fabrics use vias, on one or more mask layers, for programming.

Regardless of the fabric used, designers should be aware of a few do's and don'ts when designing configurable sections within an SoC.

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