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SystemVerilog reference verification methodology: ESL
(06/12/2006 9:00 AM EDT) Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL). While the level of abstraction required to verify the design has risen correspondingly, at every stage verification has remained a major challenge. In today’s system-on-chip (SoC) design world, a wide range of verification techniques must be linked by a reuse-oriented, coverage-driven verification methodology for effective usage. This is the third in a series of four articles outlining a reference verification methodology that covers both RTL and system-level requirements. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on the techniques recommended by the VMM for SystemVerilog for ESL verification.
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