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Articles for the Week of May. 08, 2008
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Featured Article
An Efficient Software-Hardware Partitioning for Transport Demultiplexer
In this paper, we present an efficient software-hardware partitioning for transport demultiplexer. We develop transport demultiplexer software model and simulate it on reduced instruction set computer (RISC). |
Additional Articles |
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DSP or FPGA? How to choose the right device |
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Designing Around an Encrypted Netlist: Is The Pain Worth the Gain? |
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An architecture for designing reusable embedded systems software, Part 2 |
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Asynchronous DSPs: Low power, high performance |
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Articles for the Week of May. 01, 2008
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Featured Article
System Packet Interface (SPI) 4.2 IP Core
The paper describes the architecture of a novel performance-enhanced SPI 4.2 IP Core. It also mentions, through examples and performance statistics, the improvement in the performance of SPI 4.2 data transfer as against the sub-optimal IP cores available. |
Additional Articles |
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IP Core of On-line ICA Algorithm |
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How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1 |
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The Relevance of System Design |
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An architecture for designing reusable embedded systems software, Part 1 |
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Virtual prototyping boosts model-driven Design for Six Sigma methodology: Part 3 of 3 - Design example: Electronic throttle control |
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Serial ATA and the evolution in data storage technology |
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Articles for the Week of Apr. 24, 2008
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Featured Article
SystemC Mixed-HDL IP Reuse Methodology
This paper proposes a methodology which addresses the clear needs of the ever-growing SystemC mixedlanguage designs by delivering critical capabilities, including advanced verification features such as; SystemVerilog Assertions (SVA), cover-groups, SystemC Verification (SCV), and more. |
Additional Articles |
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Development and use of an Instruction Set Simulator of 68000-compatible processor core |
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C-based coprocessor design, part 2: Datapath customization |
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What floorplan information is needed for synthesis |
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Overcome power, size and cost when developing optimized '4G' chipsets for handhelds |
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A Power Integrity Wall follows the Power Wall! |
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FPGA-based flexible Ethernet switch reduces development time |
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Articles for the Week of Apr. 17, 2008
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Featured Article
Verification of IP Core Based SoC's
In an IP-Core based SoC design. A streamlined verification and analysis flow can contribute significantly to the success of a product. A strategy is devised for a more streamlined approach in IP-core based SoC verification which helps in smooth transition from design to chip tape-out stage. |
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FPGA based Complex System Designs: Methodology and Techniques |
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C-based coprocessor design, part 1: SIMD architecture |
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Software-defined silicon: Why can't hardware be more like software? |
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DDR3 memory - How to Win with Low Power and Reduced Thermal Solutions |
