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Articles for the Week of Oct. 06, 2008
Featured Article Verifying ARM Processor We describe a methodology for verifying system-on-chip designs. Using this methodology we have tested the ARM11 series microprocessor. The test bench is designed in ‘e’ language and is a XVC. These are reusable components written in the Specman Elite e verification language that can represent either a SoC component, or an external device interfacing to a SoC component.
Additional Articles
The need to address power during manufacturing test
Audio ADC buffer design secrets: Interfacing to audio ADC sampling circuits
Articles for the Week of Oct. 02, 2008
Featured Article IP Gate Count Estimation Methodology during Micro-Architecture Phase This paper presents challenges of gate count estimation during early architecture design phase along with effective methodology. This paper is backed up with vast experience of various IP designs with logic area up-to several hundreds of kilo gates with several hundred kilo bits of memory.
Additional Articles
In multicore SOC architectures, buses are a last resort
How to transform silicon with dynamic reconfiguration
Measuring Quality in Semiconductor IP
Using micro-benchmarks to evaluate & compare Networks-on-chip MPSoC designs
Articles for the Week of Sep. 25, 2008
Featured Article Bridging the DFT and Product Engineering Gap to Achieve Early Silicon Validation This paper introduces a unified DFT - PE Methodology, aimed at providing a complete, methodical and fully automated path addressing gaps between DFT and PE team ensuring quick turnaround time in silicon validation.
Additional Articles
How to use FPGAs to develop an intelligent solar tracking system
Choosing the right low power processor for your embedded design
Enabling Robust and Flexible SOC Designs with AXI to PCIe Bridge Solutions
Implementing the right audio/video transcoding scheme in consumer SoC devices
Articles for the Week of Sep. 18, 2008
Featured Article Performance Verification Methods Developed for an HDTV SoC Integrating a Mixed Circuit-Switched / NoC Interconnect (STBus/VSTNoC) This paper presents the performance verification methods that were set up and used for a SoC recently developed at STM. The SoC is a one-chip satellite HDTV set-top-box decoder IC. It integrates many memory-bandwidth demanding IPs sharing one or two DDR2 memories.
Additional Articles
Using static analysis to diagnose & prevent failures in safety-critical device designs
How to defend against the cloning of your FPGA designs
Systolic FIR Filter Based FPGA
Speeding up the CORDIC algorithm with a DSP
Articles for the Week of Sep. 11, 2008
Featured Article An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC) This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.
A FPGA-Based Solution for Enforcing Dependability and Timeliness in CAN
Dynamic reconfiguration is transforming the embedded world
Building a configurable embedded processor - From Impulse C to FPGA
Reducing Power Consumption in a Fiber Channel Switch
Reinventing JTAG for SoC debugging