PowerPC System on Chip Strategy Closing the silicon / design productivity gap
Issue
ASICx capable of 40M gates (CU-11) Typical ASICs are << 1-2M gates No one company can generate all the IP Time-to-market dictates reusable cores
Key building blocks to reducing gap
CoreConnect bus architecture Blue Logic superstructures PowerPC core IP Application specific, reusable core IP World class ASIC methodology
Result
Highly integrated market-specific ASSP designs Accelerated development of ASSPs with equivalent expense Customer specific designs with reduced time to market and expense
