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D&R provides a global collaboration network for sharing design resources in the electronics SoC industry.

The world's largest directory of 6 500 Silicon IPs from more than 400 vendors


New Silicon IPs
  • 2.5D Vector Graphics Engine from Think Silicon
  • AXI Bus TFT LCD Controller from Digital Blocks
  • 12-Bit 300MS/s Current Steering DAC Silicon Proven in TSMC 65nm from Silicon & Software Systems
  • 6-bit, 1.5GHz 1.2V ADC for Blu-Ray in IBM 90nm from MIPS Technologies
  • Analog Front end platform for WLAN and WiMAX single and multi-channel MIMO systems, with low die-area and receive power Silicon Proven in UMC 65nm from Cosmic Circuits
  • RF 802.11 a/b/g dual-band 180 nm CMOS Radio from Wipro - NewLogic
  • Low Latency Avalon Memory Controller from Microtronix
  • High Speed Mixed Radix FFT/IFFT from Coreworks
  • SuperSpeed USB (USB 3.0) Device from PLDA
  • SuperSpeed USB 3.0 Device Controller from Synopsys
  • 12-bit 64MS/s Dual Input Pipeline ADC, silicon proven in TSMC 65nm from Silicon & Software Systems
  • 8-bit, 20 MHz, 1.2V ADC w/ 3.3 V S/H and 4:1 Input Mux in TSMC 90nm from MIPS Technologies
    Wanted IPs
  • Profibus Master (Nov. 25, 2008)
  • PLB to OCP bridge (Nov. 20, 2008)
  • 16-Bit 1 MSPS DAC (Nov. 11, 2008)
  • More ...


    • Featured Demos

  • OpenSPARC T1 from Sun Microsystems- For the first time in history, developers gain access to the chip multi-threading (CMT) technology unique to the UltraSPARC T1 processor, which is released under the GNU General Public License (GPL).
  • xIDE toolkit from Cambridge Consultants - Download the xIDE Integrated Development Environments for our XAP 16- and 32-bit processors. These IDEs let you write programs in C or Assembler and compile and run them on the built-in XAP Instruction Set Simulator.
  • DP8051 pipelined 8-bit microcontroller from Digital Core Design
  • LA16 - Synthesizable HDL Core from Evatronix
  • ARChitect™ Processor Configuration Tool Demo from ARC International - See how easy it is to create your own processor
  • PLLXpert Online from Ceva enables a designer to either create a custom PLL or alternatively download an existing PLL reference design that can be fine-tuned by the designer for a specific application.
  • On-line Evaluation and Front-End view generation for a Single-Port RAM generator targeting TSMC - 0.25 um from Dolphin Integration
  • Super-FinSim, a complete simulation environment for Verilog from Fintronic USA Inc.


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    Webcast / Podcast

    Featured Webcast

    Achieving Maximum Reuse Leverage: Lessons from benchmarking 1000+ IC projects

    Great Expectations probably describes the feeling prevalent throughout the semiconductor industry when reuse first entered the IC design paradigm more than ten years ago. Reuse was supposed to unleash huge boosts in development productivity and output that would offset the Design Productivity Gap. Has it happened? If not, why not?

    Latest Webcast

  • Next Chapter in IP: Enabling Innovation (Jan. 28, 2008)
  • A Decade in Library IP and Mixed Analog IPs (Jan. 28, 2008)
  • How to Evaluate and Choose Hard IP ? (Feb. 12, 2007)
  • How to Design Cost-Optimized Configurable Embedded Systems with ARM926EJ (Feb. 20, 2007)
  • Integrating Nonvolatile Memory in SoC Designs: Save Time and Reduce Design Costs (Jan. 23, 2007)
  • The role of virtual fabless providers for a predictable road to product (Jan. 2, 2007)
  • How to Protect Your IP Using FPGA Design Security (Dec. 19, 2006)


    • Sponsor Links

  • Register to Win an ARM926EJ Development Board
    Register to find out more about the development flow and tools supported and how you can optimize the cost and differentiate your next embedded system design.


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