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New Silicon IP
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- Certified according to ISO 26262:2018 edition series of standards
- RISC-V RV32GCBP Instructions
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20 mA LDO voltage regulator (output voltage 1.1V/1.2V/1.3V/1.4V)
- TSMC EF CMOS 55nm
- High precision stabilization voltage
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On-chip memory expansion
- On-the-fly compression / decompression of cache lines
- Optional secureTraining on metadata capability
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OTP One Time Programmable IP SMIC 55HV
- Small IP Size
- High reliability
- Radiation hardening
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MIPI C-PHY v2.0 D-PHY v2.1 for TSMC N5A
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
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Comprehensive, High Throughput Pixel Operation IP
- Memory to Memory IP
- Diverse Input/Output Formats
- Rich Pixel Processing Functions
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32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- Ideal either as a Main Controller or a Safety Island in a Functional Safety System
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Securyzr™ Intrusion Detection System (IDS)
- Part of a global threat detection, analysis and response solution form Chip-to-Cloud relying on Securyzr™ iSSP (integrated Security Services Platform).
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Ultra-small footprint, static framing, DPTx 1.4 IP core
- DisplayPort 1.4 compatible.
- Ultra-small footprint (1k LUT minimum, 3.5k LUT maximum).
- Hardware proven on AMD/Xilinx 28nm FPGA fabric.
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High Image Quality Super Resolution IP
- Up to 8K @ 60 FPS
- Up to 4 pixels per clock
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Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
- Drag & Drop Graphical User Interface
- Unified configuration tree view
- Intelligent routing path calculation
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High-Density eMRAM Compiler TSMC 22ULL
- eMRAM compiler enabling low-power designs requiring high memory capacity
Top Silicon IP
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RISC-V GPGPU for 3D graphics and AI at the edge
- Unparalleled RISC-V flexibility & programmability
- Compelling ultra-low power 3D for wearables & aiot
- Enabling your ai application without additional silicon cost
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32-Bit RISC-V Embedded Processor and Subsystem. Maps ARM M-0 to M-4. Optimal PPA.
- 32-bit RISC-V core
- 2-stage pipeline
- Available in many versions
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Fast Fourier Transform IP Core
- Supports forward and inverse complex FFT
- Supports transform length (N) from 23 to 2¹⁶
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High-performance mixed-precision NPU IP
- Matrix Multiplication: 4096 MACs/cycles (int 8), 1024 MACs/cycles (int 16)
- Vector processor: RISC-V with RVV 1.0
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64-bit, highly efficient application RISC-V CPU
- GPU integration
- Security at the forefront
- Ecosystem ready
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3.3V general purpose I/O for 28nm CMOS
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
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Ultra low power AI inference accelerator
- Energy Efficient
- High Performance
- Small footprint
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112Gbps VSR to extended LR SerDes IP on TSMC N7/N6
- Excellent performance for VSR to extended LR channels from 1G NRZ to 100Gbps PAM4 data rates
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Aeonic Generate™ AWM3
- Droop and DFS/DVFS response profile
- Programmable droop and DFS/DVFS response rate
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112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA ...
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NPU
- 20% more energy efficient than Ethos-U55 and Ethos-U65, enabling future use cases in a sustainable way.
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General Purpose Neural Processing Unit (NPU)
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
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